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Micrel
Transceiver Sync/Non-Synchronous Mode
MICRF506BML/YML
A6..A0
0000000
0000110
0000111
D7
LNA_by
-
BitRate_clkS1
D6
PA2
Mod_clkS2
BitRate_clkS0
D5
PA1
Mod_clkS1
RefClk_K5
D4
PA0
Mod_clkS0
RefClk_K4
D3
Sync_en
BitSync_clkS2
RefClk_K3
D2
Mode1
BitSync_clkS1
RefClk_K2
D1
Mode0
BitSync_clkS0
RefClk_K1
D0
Load_en
BitRate_clkS2
RefClk_K0
Sync_en
0
0
1
1
State
Rx: Bit
synchronization off
Tx: DataClk pin off
Rx: Bit
synchronization on
Tx: DATACLK pin on
Comments
Transparent reception of
data
Transparent transmission
of data
Bit-clock is generated by
transceiver
Bit-clock is generated by
transceiver
When Sync_en
=
1,
it will enable the bit
MICRF506 is defined as “Master” and provides a
synchronizer in receive mode. The bit synchronizer
clock needs to be programmed, see chapter Bit
synchronizer. The synchronized clock will be set out
on pit DATACLK.
In transmit mode, when Sync_en = 1, the clock
signal on pin DATACLK is a programmed bit rate
clock. Now the transceiver controls the actual data
rate. The data to be transmitted will be sampled on
rising edge of DATACLK. The micro controller can
therefore use the negative edge to change the data
to be transmitted. The clock used for this purpose,
BITRATE_CLK, is programmed in the same way as
the modulator clock and the bit synchronizer clock:
data clock that allows users to utilize low cost micro
controller reference frequency.
The data interface is defined in such a way that all
user actions should take place on falling edge and is
illustrated Figure 9 and 10. The two figures illustrate
the relationship between DATACLK and DATAIXO
in receive mode and transmit mode.
MICRF506 will present data on rising edge and the
“USER” sample data on falling edge in receive
mode.
DATAIXO
f BITRATE_CL K =
f XCO
Refclk_K × 2 (7 - BitRate_cl kS )
DATACLK
where:
f BITRATE_CLK : The clock frequency used to
control the bit rate, should be equal to the bit
rate (bit rate of 20 kbit/sec requires a clock
requency of 20kHz)
f XCO : Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1
and 63
Figure 10. Data interface in Receive Mode
The User presents data on falling edge and
MICRF506 samples on rising edge in transmit mode.
DATAIXO
DATACLK
BitRate_clkS:
Bit rate setting,
values
Figure 11. Data interface in Transmit Mode
between 0 and 6
Data Interface
The MICRF506 interface can be divided in to two
separate interfaces, a “programming interface” and a
“Data interface”. The “programming interface” has a
three wire serial programmable interface and is
described in chapter Programming.
The “data interface” can be programmed to sync-
/non-synchronous mode. In synchronous mode the
When entering transmit mode it is important to keep
DATAIXO in tri-state from the time Tx-mode is
entered until user starts sending data. The data is
provided directly to the modulation circuit and
violation of this may/will cause abnormal behavior.
Depending upon the chosen FSK modulation, some
sort of encoding might be needed. The different
modulation types and encoding is described in
chapter Frequency modulation.
July 2006
19
M9999-092904
+1 408-944-0800
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